Beyond Multicore CPUs

Think about the common processing issues you have with the servers in your

data center: the inability to add specialized processors to handle different

kinds of workloads, floating point precision errors when doing financial

calculations requiring further adjustments and problems of compatibility and

interoperability between what you had and what you want to have.

Some of the processors that are slated for imminent release through 2007 and

early 2008 include a bundle of new technologies that will make



these problems a thing of the past. These processors are spread across both the
x86 and non-x86 platforms. This story looks at these technologies and the

benefits they will provide to you.

Decimal math



As kindergarten kids, we learnt how to count and do things with numbers using
our ten fingers. Ancient mathematicians translated this into decimal

mathematics. The infamous original Pentium 1 floating point precision error

proves dramatically fatal when you use computers to calculate missile firing

tables, launching spacecraft, synchronizing automatic medication equipment or

robotic surgical arms, performing year end financial calculations and the like.

This was because it had a floating point bug related to dividing two decimal

system numbers using binary math.

New CPUs like the expected IBM Power6 processor will include the ability to

do math within the processor using the decimal number system (1,2,3,...) instead

of the binary (0s and 1s). It is easier and faster for the processor (being an

electronic state device) to process 1s and 0s against decimal numerals and math,

and binary will still be the way it does all other processing.

CPU-based VMX



Also known as AltiVec, this is an instruction set that can apply a single
processing instruction to multiple data elements. This finds varied usage in

servers: one can use it to perform business data analysis, genetic data

processing as well as backend video and audio rendering. The technology was

created by Freescale and implemented as VMX by IBM and as Velocity Engine by

Apple. The instruction set, though developed in the late 1990s, was used by a

variety of applications including Adobe Photoshop, Mac OS X, iTunes and

QuickTime, will be seen for the first time in a server-class CPU, the IBM

Power6.

Hot spare cores



Hot sparing, as you know, is the technology that lets you switch to a secondary
component while the system is turned on and functioning without needing to bring

down the system to make the switch. So far, we've seen this applied to

storage, power supplies and memory. Now, you can hot-spare processor cores as

well.

The system automatically and continuously monitors data in the processor

cache. When errors are detected, attempts are made to reload the data and

continue or repeat the last instruction step. If further errors are encountered,

the entire core is hot-spared to a new core in the server and an alert is raised

to the server administrator to troubleshoot the problematic processor or core.

Innovation Socket



While Intel has been busy stuffing as many cores into a single die as can be
done, AMD decided to simply add more processor sockets to their motherboards and

open up the socket specification. This would let you add specialized processors

into sockets you are not plugging multi-core Opteron chips into. Such chips are

envisaged to be dedicated encryption/decryption engines and Java processors

among other possibilities. So, you would take a '4x4' board (as they are

called), add say two Opteron dual cores and one Java processor and increase the

computing power of your server manifold if your processors spend a lot of time

otherwise doing Java. AMD calls this capability 'Torrens' and this kind of a

socket the 'Innovation Socket.'

Time for standardization



The industry has agreed that multi-core hardware and software today are built
around proprietary specifications and realizes that there is a need for a more

'heterogeneous embedded distributed system.' The body behind this is called

the 'The Multicourse Association,' and they are working towards standards to

create programmable application interfaces (API) for resource management,

communication and transparent inter-process communication.

To contribute to this, the EMBC (Embedded Microprocessor Benchmark

Consortium) has started work on building some kind of benchmarking and

assessment methodology for multi-core processors. These tools are expected to

become available as early as Q2 of 2007. For now the EMBC's focus will be on

building tools to assess the same kind of cores in a system (eg: all dual core

chips) as against different kinds of cores (eg: a dual core and a quad core) in

the system.

Mind the memory



Consider a server with 8 CPUs with two cores each, making for a total of 16
processing cores. Now, how would this system ensure trouble and error free

memory access? If you also consider technologies like AMD's Direct Connect

Architecture (discussed last month, Pg 54) which lets the processor core manage

memory via the HyperTransport Controller rather than using a Memory Controller,

the situation gets complicated as you increase the number of cores.

To help ease the situation, processors like IBM's Power6 will use a

two-layer mechanism to inter-communicate. Here each core would bond directly

(core to core) to three other cores on one layer, each of this group of four

cores would connect to seven other groups (a total of eight core groups or 32

cores in all) using a second layer. This, they say, will keep their cache

memories in sync.

Stay tuned to this series for more on the latest technologies as well as the

technology behind the buzzwords rolling out to power processors of the



future.