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More life for Silicon

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PCQ Bureau
New Update

Faster, more powerful and better is the motto that every chipmaker has faithfully followed for the last few decades . However, barriers have been reached, especially with conventional microprocessors that are made up of thousands of silicon-based transistors. The physical limitations of miniaturizing compo- ents further have made many prophesise the end of Moore’s Law and the end of silicon-based processors. Recent efforts in strained-silicon technology by IBM, Intel, Taiwan-based UMC and American start-up AmberWave, might keep Moore’s Law on course for a few more years, till we shift to now much hyped concepts of nano- and DNA-computing . 

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The atoms of Silicon and

Silicon-germanium lattices before and after sandwiching them together 

For about four decades, chipmakers have pushed performance and capabilities by packing more and more transistors on to silicon wafers, which also meant smaller and smaller transistors. But, increasing performance by shrinking transistors has reached certain physical limitations now. Miniaturization has reached nano levels, where atomic forces interfere with the flow of electrons through the transistors, which forms the basis of a chip’s computational power. Here, known laws of physics in the normal world no longer apply. However, researchers say that better performance and, hence, more energy efficiency is possible by reducing these forces. Strained silicon, thus, emerged as an alternate to increase chip perfor mance in the interim period before powerful alternates like nano-computing and DNA computing become a reality. 

Strained-silicon technology envisages stretching silicon atoms by placing a layer of Si-Ge (Silicon-Germanium) below. The stretching (see diagram) is a result of the tendency of atoms in a compound to align with one another. IBM scientists say that this ‘straining’, decreases resistance and allows the electrons to flow up to 70 % faster and, thus, forecast chips that are 35% faster than current ones without shrinking transistors. At the same time, production costs are expected to rise only by about 2—3%, since manufacturers can use a large part of their existing fabrication units.

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The major players claim success based on their vision of the market. IBM wants to take advantage of both strained silicon and existing SOI (Silicon-on-insulator) technology. IBM’s chips will be based on the 65 nm node (about two chip generations away) while AmberWave expects to license its chips both in the 90 nm and 65nm range. Strained silicon is also expected to appear in Intel’s 90 nm Prescott chip sometime in 2003. Meanwhile, start-up AmberWave has claimed success in commercializing the technology and had licensed it to AMD in 2002. However, in January 2003, AMD also entered into a new deal with IBM (AmberWave’s competitor) for working on strained silicon at 65 and 45 nm levels, throwing a question mark on its previous deal. 

Though technology predictions are always hotly debated, we’ll assume that 2005 will see the emergence of 10 GHz processors, leaving aside cooling issues. IBM estimates that the shift from about 6 GHz onwards will require strained silicon.



So, silicon seems to have quite a bit to go before yielding to other competitors like carbon nanotubes or DNA. But, that said, rapid and often unpredictable changes in technology make an exact roadmap difficult to foresee. We’ll have to just wait and watch in the meanwhile.

Benoy George Thomas

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