by June 2, 2003 0 comments

The chipset of a computer works much in the same way as a city’s road infrastructure. As in most modern cities, it’s not the cars that keep people from driving fast, but the congestion on the roads. Similarly, no matter how fast the individual components of a computer might be, if the chipset that ties them together isn’t top notch, the chances are that your computer will be slow. 

Intel is moving out to another city. The 850E has been the chipset of choice for a few years now, but is clearly showing signs of age. Technologies like Serial ATA, on-board RAID, 5.1 sound, AGP 8x, DDR-400, gigabit Ethernet and higher FSBs demand a stronger platform. The solution to these is the 875P. Let’s see what this latest chipset from Intel is made up of. 

The MCH 
Intel’s North Bridge, the MCH (Memory Controller Hub), is going to see quite a bit of change. Perhaps the most important change is the transition to a 200 MHz quad-pumped FSB (Front Side Bus). The P4 processor, with its high clock speed and long execution pipelines, enjoys high memory bandwidth and has already seen an upgrade to 533 MHz from the 400 MHz it was debuted at. From now, Intel’s processors will feature an even higher 800 MHz (effective) FSB. A 3.0 GHz CPU with a 15x multiplier has already been introduced.

Intel has also seemingly bid farewell to Rambus. For the 875P features a DDR-400 interface. This is the latest DDR memory in the market and has also come far from the 200 MHz it was debuted at. However, this is not all that is special about
Canterwood’s memory support. Gaining inspiration from NVIDIA’s nForce chipsets, Intel is now equipping its chipset with a dual-channel memory bus. If you do the math, you’ll see that the FSB and the memory bus are now both synchronized perfectly at 6.4 GB/s, considerably more than any of the past chipsets. For example, the 845PE (Intel’s DDR chipset for the P4) was limited at just 2.7 GB/s of memory bandwidth.

The AGP interface has been upgraded to 8x capability. While the performance difference between 8x and 4x are close to negligible right now, future graphics cards should be able to utilize this additional bandwidth quite well. Also to be kept in mind is the fact that the 875P will be the flagship chipset for a few years now, so having some headroom is not a bad idea.

Finally, another big change to the MCH is related to networking. Gigabit Ethernet equipment is quickly becoming popular, and can be quite a headache for chipset designers. This is so because the total bandwidth present between the MCH and the ICH (South Bridge) is 266 MB/s. Passing a gigabit of Ethernet data can quickly saturate this bandwidth and leave little room for other communications (PCI, USB, etc). Intel’s solution? Networking now has a whole new bus dedicated for itself. Called the CSA (Communications Streaming Architecture), the North Bridge is now directly linked through this bus to the network chip, thus sparing Intel’s Hub-Link (the interconnect between the two bridges). 

The ICH 
ICH5 (I/O Controller Hub) for the 875P also has several new features. It has finally been decided that eight USB 2.0 ports ought to be enough for everybody, so that is the number that will be supported. Also, with the current transition to Serial ATA, Intel has decided to include such controllers on the chipset itself. The Serial ATA controller has been moved off the PCI bus and now has a direct link to ICH5. This helps in reducing the congestion on the PCI bus. There is RAID support built-in as well. Currently, only RAID 0 is supported, but RAID 1 should also be possible through a BIOS update.

Anuj Jain

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