AI broke the old chip playbook: AMD is writing a new one

AI did not wait for invitation. It showed up everywhere at once. Phones, PCs, servers, data centers. What began as a software-driven shift is now reshaping hardware itself, forcing chipmakers to rethink how AI chips are designed, connected, and scaled. In a conversation with PCQuest, Chetan Hingu, Head – Inside Sales (Asia Pacific & Japan) | Commercial Business Strategy & Value Business (India), AMD, explains why this transition feels different from earlier cycles. AI is not moving in stages. It is landing across consumer devices and data centers at the same time, pushing long-term silicon decisions into the present.

Why AMD is doubling down on chiplet design for AI chips

Chiplet design has quietly become one of AMD’s biggest advantages in the AI chip race. While monolithic dies struggle with scale and yield, chiplet-based CPUs allow compute, cache, and input/output (I/O) to evolve independently.

For AI workloads, that flexibility matters. Training, inference, and traditional enterprise tasks all place different demands on silicon. AMD’s chiplet architecture makes it easier to tune performance per watt while scaling core counts, which is increasingly important for AI data center chips. This approach is already visible across AMD EPYC processors used for AI inference and preprocessing, where chiplets help balance performance, efficiency, and cost at scale.

The convergence of CPU, GPU, and NPU in the AI era

AI workloads no longer live in one place. Heavy training jobs still lean on GPUs, but inference, orchestration, and everyday AI tasks are spreading across CPUs and NPUs.

This is where the roles of CPUs, GPUs, and NPUs start to blur. High-performance accelerators handle parallel workloads, while CPUs increasingly manage AI workload orchestration. Integrated NPUs are stepping in to handle local AI experiences such as assistants and on-device inference.  The result is a more layered AI hardware stack, one where AMD EPYC CPUs, AMD Instinct GPUs like the MI325X, and integrated NPUs each play distinct but connected roles.

When wires hit the wall: Infinity Fabric and the future of AI interconnects

As AI systems scale, interconnects become just as important as compute. AMD’s Infinity Fabric has long been central to its multi-die strategy, enabling fast communication between chiplets and processors. But electrical links have limits. At high data rates and core counts, signal integrity and power density become bottlenecks. These challenges show up most clearly in AI training, high-performance computing, and in-memory analytics.

That is why advanced options such as three-dimensional (3D) fabric interconnects and even optical interconnects are now part of long-term discussions. The shift will not be driven by hype, but by clear gains in throughput per watt and system-level efficiency.

Open source AI ecosystem: why ROCm matters more than ever

Hardware alone is not enough. AI performance increasingly depends on how well software stacks exploit underlying silicon. AMD’s ROCm platform plays a critical role here, positioning itself as an open source AI ecosystem that supports AI workload orchestration across CPUs and GPUs. For developers looking beyond proprietary toolchains, ROCm is becoming a serious alternative for deploying AI workloads at scale.

This hardware-software co-design approach is especially important as AI models grow larger and more complex, demanding tighter integration between compilers, libraries, and silicon.

What runs where: distributing AI workloads between CPU and GPU

As AI spreads, the real question is not whether acceleration is needed, but where it belongs.  During sudden demand spikes, such as national elections or major events, AI workloads behave very differently. Some tasks are efficiently handled by AMD EPYC CPUs, while others benefit from scaling out on AMD Instinct GPUs, where parallelism dominates.

On the client side, integrated NPUs increasingly handle local AI experiences, keeping interactions fast and responsive. Heavier analysis quietly shifts back to the data center. This ability to distribute AI workloads between CPU and GPU, and move them dynamically, is becoming a defining feature of modern AI system design.

Why integrated NPUs are shaping local AI experiences

Not every AI task needs a data center. Integrated NPUs are now good enough to handle chatbots, assistants, and personalization workloads directly on the device. By keeping these tasks local, systems reduce latency, improve privacy, and lower power consumption. This shift toward integrated NPUs for local AI experiences is quietly changing how PCs and edge devices are designed.

AI is no longer just about raw compute. It is about delivering the right experience in the right place.

How AMD decides which AI features belong in silicon

Not every AI feature deserves to be etched into silicon. The pace of AI research makes long-term bets risky. AMD looks closely at real-world usage patterns, especially in industries such as healthcare, pharmaceuticals, and enterprise IT. Workloads like AI-driven drug discovery place specific demands on floating-point performance, memory access, and interconnect bandwidth.

By tracking these trends, AMD aims to focus on AI features that have lasting value, rather than chasing short-lived optimizations.

Why AMD is playing the long game in AI hardware

Semiconductor research moves slowly. AI moves fast. Bridging that gap is the real challenge. AMD’s long-term AI chip strategy focuses on performance, energy efficiency, and platform flexibility. From chiplet architecture and Infinity Fabric to ROCm and future interconnects, the goal is to build hardware that adapts as AI workloads evolve.

The old chip playbook no longer applies. AI has rewritten the rules, and the next decade of computing will be shaped by how well silicon keeps up.

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