by June 2, 2003 0 comments



Acomputer system is made up of different components, such as the CPU, RAM, hard disk, keyboard, modem and network card. All these components need to communicate with each other in order to perform the functions of the system. To communicate, they use a channel or a set of wires called a bus. So, the bus is the path between the different parts of a computer. There are different types of buses performing functions at different levels in a system. There are two main buses: one is the system bus (also called the local bus), which connects the CPU to the system memory, and other is the shared bus, which connects additional components, such as the modem, network cards and sound cards. This is called a shared bus because it lets multiple devices connect to the CPU and memory using the same path. 

Evolution of the Bus
Earlier PCs came with the ISA shared bus, which operated at a speed of 8 MBps, and later at 16 MBps. ISA was a popular bus standard and was used in PCs for a long time. Although it is no longer popular, you can still find some manufacturers putting ISA slots on their motherboards. After the ISA standard, another standard called EISA emerged, with a speed of 32 MBps, but it did not become very popular. After this came the VL-Bus or the VESA (Video Electronics Standards Association) local bus. This bus is different from the other buses. It is a 32-bit bus that gives direct access to the system memory at the speed of the processor. This bus tied into the CPU, but connecting more than two devices to the VL-Bus caused interference with the performance of the CPU. So, this bus was used to connect graphic cards to the CPU. Although the bus operated at a speed of 132 MBps, it never became a big success. 

 

PCI express (earlier known as 3GIO) interconnects the North and 
South Bridge and replaces Intel’s Hub Link architecture. It also provides 
connections for AGP, expansion cards and attach points for 
USB 2.0, FireWire, and Gigabit Ethernet

In 1992, Intel introduced a new bus design, which was called PCI (Peripheral Component Interconnect). This bus is not a replacement of the ISA bus, but it lets you put the ISA bus along with it on the motherboard. So, you can have systems with both the PCI and the ISA bus. PCI originally started at 133 MBps with the revision 2.0. Then came PCI 2.1 at 266 MBps, followed by PCI 2.2 at 533 MBps. The latest revision of PCI is PCI-X, which provides for 64-bit data transfer at 133 MHz giving a whopping 1GBps transfer rate. 

PCI is the most widely used bus in PCs and servers today. But the need for video and fast graphics required an even faster interface than the PCI. In 1996, Intel introduced another bus designed for high-end graphics. This was called AGP (Accelerated Graphics Port), which is a point-to-point connection between CPU/memory and graphics card. So, unlike the PCI bus, which is shared by many devices, the AGP bus connects only the graphics card to the system. AGP gives faster performance over PCI as well as direct access to the system memory. Original AGP 1x specification has a transfer rate of 266 MBps, with the latest AGP 8x having 2.08 GBps transfer rate. This high bandwidth is sufficient for real-time video and games.

An example of Hypertransport architecture used to interconnect multiple processors

Which bus goes where
How do buses fit on a computer motherboard? In the first diagram, you can see two chips, the Northbridge and the Southbridge, with the PCI bus connecting them. So, PCI acts as a chip-to-chip bus. PCI also acts as an expansion bus for adding expansion cards, such as the sound card, modem and network card. The Northbridge connects to the graphics device via the AGP bus and the CPU via the system bus. But, now PCI is being replaced by proprietary architectures for interconnecting the Northbridge and the Southbridge. These include Intel’s Hub Link, which was introduced with Intel’s 800 series chipsets, VIA’s V-Link and
SiS’ MulTIOL.

Now, it seems that even PCI is becoming a little slow at handling devices, because the devices that connect to it–Gigabit Ethernet cards, GHz+ CPUs, fiber channel and Ultra 320 SCSI–are becoming more resource hungry. These devices require higher bandwidth and lower latency interconnects. Even desktops with their requirements for high-speed video and 3D graphics require something better than the now old PCI. Various organizations and groups are pushing in new designs and standards to meet these requirements. Each of these new technologies has something in common with the other and in some cases they complement each other. Two technologies being talked of are PCI Express and Hypertransport. Both promise to deliver high-speed connections between devices so that the communication path does not become the bottleneck in overall system performance, as with
PCI.

PCI Express or 3GIO
PCI Express is the official name of the architecture formerly code named Third Generation I/O or 3GIO, and introduced by Intel. The PCI-SIG (Special Interest Group) has made PCI Express the successor to PCI for PCs and servers. PCI-SIG is the industry organization chartered to manage and develop PCI specifications. 

PCI express is meant to replace Intel’s Hub Link architecture and is meant for chip-to-chip interconnects, AGP, expansion card connections and even an attach point for USB, FireWire and Gigabit Ethernet. As there are still too many PCI cards in the market, it is first expected to appear as the chip-to-chip interconnect and attach point with a bridge for PCI expansion cards.

The major difference between PCI and PCI Express is that while PCI is a parallel, shared bus, PCI Express is a point-to
point, serial and packet-based interconnect. Compared to the shared, parallel bus architecture, point-to-point permits each device to have a dedicated link, without arbitrating for a shared bus. Parallel buses require stringent synchronization methods as parallel bits arrive at different times. This takes out the benefit of parallel data transfer so serial connections offer higher bandwidth with fewer signals. This leads to small connectors and smaller form factors. Serial links also do not have the problem of crosstalk, EMI unlike with parallel links. A single PCI Express link is made up of two unidirectional links with separate receive and send signal pins. The initial signaling speed is 2.5 Gbits/sec per wire pair in each direction. Future versions may be offered at 5 Gbps. There can be a total of 32 such serial links between devices allowing for high bandwidth devices.

Systems with PCI Express will have a different design. It will consist of an I/O bridge, a switch and I/O device endpoints. The switch provides direct point-to-point connections for devices attached to it as well as peer-to-peer communication for them.

HyperTransport
Introduced by AMD, HyperTransport is now managed by the HyperTransport Technology Consortium. While PCI express is aimed at PCs and servers, HyperTransport is aimed at communications and embedded systems. HyperTransport can also be used as a chip-to-chip, chip-to-I/O, and processor- to-processor connection for multiprocessor configurations. nVidia’s nForce/nForce2 chipsets use HyperTransport as a chip-to-chip connection and is even being used in Microsoft’s Xbox with an Intel processor. Like 3GIO, it has
a point-to-point packet-based interconnect between devices.

Each connection is made of two unidirectional links (one for send and one for receive) with each having a speed of 1.6
GBps.

There can be a total of 32 such connections giving an aggregate bi-directional bandwidth of 12.8 GBps. HyperTransport also permits daisy chaining of up to 32 devices.

One of the differences between PCI Express and HyperTransport is multiprocessor interconnect. PCI Express is not meant for processor-to-processor communication, whereas HyperTransport provides high-speed inter-processor interconnect for AMD’s latest line of 64-bit Opteron CPUs. The Opteron has the NorthBridge logic built inside the CPU core, with an MCT (Memory Controller), HyperTransport interface for inter-processor communication and HT (Host Bridge) for I/O devices.

The four processors as shown in the picture are connected by point-to-point HyperTransport links and do not share data over a central system bus, thus eliminating problems of arbitration and improving performance. The data is transferred from one processor to the other through direct links and switching.

Both bus technologies have a single aim of improving speeds while transferring data from one system component to the other.

The two technologies have some common application areas like chip-to-chip communication, where both of them can be used, and some separate application areas like inter-processor communication in HyperTransport. PCI Express is the successor to PCI, so you may even find systems with both technologies complementing each other at different levels. One case may be where PCI Express is used for expansion, chip-to-chip interconnect and HyperTransport for multiprocessor interconnect in large servers. How the computing world benefits from these two amazing technologies still remains to be seen.

Anoop Mangla

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