PCI-Express

Earlier known as 3GIO or Third Generation IO, PCI-Express is the successor to the PCI bus, as defined by the PCI special interest group. PCI-Express is a serial interface resulting in point-to-point high speed link for each device and maintains
backward compatibility with PCI applications and drives. 

The PCI bus has been around since 1990 in both desktops and servers. Several variations and versions of the standard were also developed such as PCI-X and PCMCIA to cater to different requirements. The PCI bus provided up to 133 MB per sec of shared throughput. Though, it has been sufficient so far it won’t be anymore, with emerging technologies such as Gigabit Ethernet, high performance graphics and RAID because of higher bandwidth requirement. This is where PCI-Express comes in. 

The basic architecture of PCI-Express consists of a host (memory) bridge and several end points (I/O devices). A new element called ‘switch’ is introduced into the I/O system for multiple point-to-point connections. A PCI-Express link consists of dual simplex channels, each consisting of two low-voltage differential pairs of signal. In this approach the signal is sent from source to receiver over two lines. One contains a ‘positive’ image and the other, a ‘negative’ or ‘inverted’ image of the signal.

The lines are connected using strict routing rules so that any noise that affects one line also affects the other. The receiver collects both signals, inverts the negative image back to the positive and adds the two collected signals, which efficiently removes the noise if introduced. 

The interconnects marked in pink will be the PCI-Express links. Notice that it also extends to the graphics sub-system, meaning a changeover from AGP

As PCI-Express is a point-to-point architecture, the entire bandwidth of each PCI-Express bus is dedicated to the device at the end of the link. Thus, multiple PCI-Express devices can work without interfering with each other. PCI-Express link supports x1, x4, x8 and x16 lane widths. The fundamental ‘x1’ link has peak raw bandwidth of 2.5 Gbps. And since, the bus is bidirectional, the effective raw data transfer rate is 5 Gbps. Similarly, for the x4 effective raw data transfer is 20 Gbps, x8 is 40 Gbps and x16 is 80 Gbps. PCI-Express will also be able to hold Hot Pluggable/Hot Swappable devices. 

PCI-Express provides a reliable and scalable high speed serial interconnect that will support an extensive range of platforms, servers, desktops, mobile, embedded device and workstations. Moreover, PCI-Express will be software compatible with all existing PCI based software to facilitate smooth integration. Gradually, it will also replace the PCI, PCI-X and AGP parallel buses and is expected to be available towards the second half of this year. A number of PCI-Express form factors will be available, and the working group for PCI wants to ensure that PCI-Express architecture based systems don’t cost more than existing PCI based products. But then the real pricing will be known only once the products actually arrive.

Sushil Oswal