Power on the Move

Life minus a mobile phone is simply unimaginable. We all need mobiles, not
only to talk and SMS, but also to store numbers, set reminders, alarms, surf
websites, listen to music, click pictures, and so on. Gone are the days when
mobile phones were meant only for phone calls. Today, nobody buys a mobile phone
just for phone calls! In fact there would hardly be a model available that would
offer just that. Even low cost mobiles today come loaded with features. All this
implies that the processors inside mobiles need to be extremely smart to handle
complex applications and multitask, without compromising on call quality. With
increasing demand, the mobile phone architecture has also undergone major
modifications.

Unlike its big daddies-the desktop and server processors, a mobile phone
processor needs to be cost effective and also be able to dish out tons of
functionality, without consuming too much power. As an example, let's consider
the scenario, where the entire processing power of a cell phone is being
consumed by a certain application and the cell phone receives an SMS. You need
more power to run the SMS, and if simultaneously the phone starts ringing, then
it's curtains for the processor.

So, a processor should be perfectly capable of performing multiple tasks at
all times. This is especially true in Windows based mobiles, as the Windows OS
would itself stress the processor to a great extent. So, like desktop and server
processors, even a mobile processor has to generate great computational power.
We shall now discuss what these processors need to have to enable them to
deliver so much compute power. We also provide you with a small snippet of all
application platforms that are available in the market and which enable
developers to develop applications that can stress the processor to its limits.

The Nokia N95 is based on the ARM II family of processors and comes loaded with maps, office suites, browsers, etc

Mobile processors and RISC

Most current mobile processors are based on the RISC (Reduced Instruction
Set Computer) platform. So it's important to understand RISC in order to get an
in-depth knowledge of mobile processors. RISC is a CPU design that emphasizes on
simple instructions that do less but still provide higher performance, if this
simplicity can be utilized to make instructions execute fast. It was devised in
1970s when it was felt that compilers at that time weren't able to take full
advantage of features that would ease coding. It was decided that such functions
could be carried out by a sequence of simpler instructions, if this could enable
implementations which are simple enough to cope with high frequencies and small
enough to allow many registers.

The main goal was to make instructions so simple that they could easily be
pipelined to achieve a single clock throughput at higher frequencies. Some of
the well known RISC families are DEC Alpha, ARC, ARM, AVR, MIPS, PA-RISC, Power
Architecture and SPRAC. Around 75% of the embedded 32-bit RISC CPUs are from
ARM, based on different generations of ARM design architecture. The CPU is a
32-bit RISC processor architecture that is widely used in a number of embedded
systems. The best thing about ARM CPUs is that they are very power efficient,
making them an ideal choice for mobile devices where small battery sizes make
power consumption a critical factor.

Mobile processor architecture

ARM design saw light of the day in 1983 as a development project at Acron
Computers Ltd. Over the years many samples were designed. The first real
production system was ARM2, which was probably the simplest and most useful
32-bit microprocessor with only 30,000 transistors. It was considered the
simplest 'coz it didn't have any microcode.

Nokia's N Gage is based on the ARM 9E family, majorly around the ARM v5TEJ architecture

The ARM architecture includes some of the RISC features such as no support
for misaligned memory access, load and store architecture, orthogonal
instruction set, large 16x32 bit register file and mostly single cycle
execution. In 1980s, Apple Computers started working with Acron on a new version
of ARM core. Thus ARM6 was born and Apple used the ARM6-based ARM10 as the base
for their Apple Newton PDA in 1991. Even though the ARM architecture has changed
over the ages, its core has remained largely the same size.

ARM2 had 30,000 transistors while ARM6 grew only to 35,000. The common
architecture supported on smartphones, PDAs and other handheld devices is ARMv4,
even though Apple eMate300 was based on the ARM7 family of ARMv3 architecture.
Nokia N-gage phone, which was a rave for its design, was based on ARMv5TE
architecture with ARM946E-S core design having enhanced DSP instructions and
very tightly coupled memories.

The Sony Ericsson K and W series phones are based on ARM9E family built
majorly around the ARMv5TEJ architecture. Along with enhanced DSP instructions
this architecture also has Jazelle DBX, which is meant to execute Java bite
code. It typically functions at 220 MIPS at 200 MHz. Even Siemens and BenQ (X65
series and newer) are also based on the same architecture and belong to the same
ARM series.

One would notice each family having various architecture, which will have
different core designs and instruction sets functioning at different MIPS. HTC
Universal, Blackberry 8700, Blackberry Pearl (8100) all belong to the XScale
architecture designed on ARMv5TE architecture but have different cores.

HTC Universal is based on PXA27x core and has application processor
instructions whereas Blackberry is based on the PXA900 core and doesn't have
application processor instructions. Recently Nokia launched their latest N95
model with 'This is what the computer has become' tag line, implying they wanted
to emphasize various tasks that you can do with the Nokia N95.

The N95, N93 and N800 are based on the latest ARM11 family. Even the Apple
iPhone is based on the same family of processors. It's just that the core design
is different along with a couple of instructions. The next generation of this
family is Cortex and will feature various architecture and core designs along
with advanced instruction sets.

The enhanced instruction set is what distinguishes Apple's iPhone from others, and it is again based on ARM II family of processors

Mobile Extreme Convergence (MXC) architecture

The MXC architecture promises to simplify smart wireless devices. It
separates the two main domains of a cell phone: a modern core that communicates
with the base station and an application core that powers user experience. The
benefit of separating the two cores is that now a designer can create new
applications as quickly as they're required, as they don't disturb the modern
core. An open operating system approach lets software developers deploy
applications across a broad range of devices. The key advantage with MXC is the
efficient shared memory system which provides the flexibility to partition tasks
between MCU and DSP. It also has the advantage of lower power design and
enhanced security architectures such as SIM lock, program and data integrity and
hardware features to support digital rights management.

Instruction sets in ARM

An instruction set enables a processor to perform different tasks. It also
helps to differentiate each processor within a particular family from the other
in terms of overall functionality. So it is important to know what exactly the
instruction sets do.

Thumb: It is a compressed instruction set which uses 16-bit
instruction encoding but still processes 32-bit data. Here, smaller opcodes have
less functionality.

DSP Enhancement Instructions: These have mainly been incorporated to
improve ARM architecture for digital signal processing and multimedia
applications. One can easily identify the architecture with such an instruction
set by looking for 'E' at the end of the name of the architecture as in ARMv5TE.

Jazelle: Jazelle DBX (Direct Bytecode eXecution) allows ARM
architecture to execute Java byte code in hardware as another execution state
alongside the existing ARM and Thumb state. It is mainly used by mobile phone
makers to increase the execution of Java ME games and applications.

Thumb2: Announced in 2003, it extends the limited 16-bit instruction
set of Thumb with additional 32-bit instructions, mainly to increase the breadth
of the instruction set. All ARMv7 chips support Thumb2.

Advanced SIMD: Marketed as NEON, this is a combined 64 and 128-bit
SIMD (Single Instruction Multiple Data) instruction set that provides
standardized acceleration for media and signal processing applications.

VFP: It provides low cost single precision and double precision
floating point computation. It also supports execution of short vector
instructions, which is useful in graphics and signal processing applications by
reducing code size and increasing throughput.

Security Extension (TrustZone): It provides a low cost alternative to
adding an additional dedicated security core to an SoC, by providing two virtual
processors backed by hardware based access control.

Conclusion

The onslaught of smart phones has led to clamours for processors with
multitasking capabilities. The market promises to evolve in the coming months,
throwing challenges in front of the developer and the chip manufacturer to come
up with more enhanced solutions. The processors within a mobile phone will
witness major upgrades with newer instruction sets and core designs been
planned. So, it will be interesting to see how far the processor can be stressed
before it reaches its saturation point.