by May 11, 2002 0 comments



For desktop computers, performance is mostly a function of the processor, RAM, hard drive and, in case of 3D applications, the graphics card. The performance difference between different motherboards and chipsets is usually so small that it’s mostly ignored in the buying decision. When talking about servers, however, the picture is very different. Bandwidth is a huge consideration and can influence, say, how quickly a Web server processes requests. RAID arrays can saturate their data pipes, gigabit Ethernet cards can outpace the PCI bus and the connection between the North and South bridges can become a bottleneck. Chipset support is also needed for multiple processors, the memory interface, on-board RAID, sound, etc. In short, the chipset to use on the server motherboard is a very critical decision. In this piece, we will look at two new entrants in this space
The AMD 760MPX and Intel E7500 are two chipsets that have recently been introduced for the low-end segment of the market. These are for low-cost servers that do not run on a very high load and do not require the features that are present in costlier options like ServerWorks. However, this is pretty much where their similarity ends. The two use quite different technologies and don’t even support the same processors! 

AMD 760 MPX
A little history is in order before we delve into the intricacies of this chipset. The 760 MPX is actually the successor of the AMD 760 MP; a chipset introduced circa October 2000 for multiprocessing with Athlon MP processors. This chipset had two inherent limitations: the absence of a 66 MHz, 64-bit PCI bus (it had a 33 MHz, 64/32-bit bus), and the same slow PCI bus was connecting the North and South bridges. This led to a net bandwidth of 266 MB/s between the two chips, which is very low for servers. 

The 760 MPX addresses both these problems. The FSB (Front Side Bus) is used by processors to connect to the North bridge (AMD 760) of the chipset. AMD’s implementation of the bus (known as EV6) uses point-to-point protocol. What this means is that the two processors on a multi-processor system can communicate with each other without going through the main memory. This saves memory bandwidth and is considered to be the faster solution. 

The PCI bus that connects the North and South bridge has been upgraded to a 66 MHz, 64-bit bus and thus now gives a total bandwidth of 533 MB/s, which is more than enough for small servers. This bus supports two 32/64-bit PCI devices that operate at either 33 or 66 MHz. However, the bus also limits itself to the speed of the slowest device on it. What this means is that if you plug in a 33 MHz, 32-bit device on this bus, its bandwidth will reduce to 133 MB/s thus harming communication between the two bridges. 

The new AMD 768 South bridge replaces the AMD 766 that was used with the AMD 760. This chip controls the second PCI bus for the chipset, which runs in the 33 MHz, 32-bit configuration. There is also an integrated AC97 audio support. 

Intel E7500
The E7500 is designed for Intel’s Xeon processors with 512 KB L2 cache. It’s North bridge, or as Intel likes to call it, the Memory Controller Hub (MCH), has quite a lot of new features. The first and foremost is the introduction of a dual-channel DDR SDRAM memory controller. While Intel has been pushing RDRAM in a big way on the desktop, DDR makes more sense on servers because of its much lower cost (since servers usually have many gigabytes of memory, the price difference between the two memories can lead to a significant difference in the overall cost). 

A chipset includes two individual chips, the Northbridge and the Southbridge

While DDR memory is available in two speeds, 200 and 266 MHz, Intel has chosen to go along with the slower of the two. This is because 200 MHz DDR memory yields a net bandwidth of 3.2 GB/s on dual channels, and this is exactly the same as the bandwidth provided by the FSB. Since synchronous operation leads to lower latency memory/CPU accesses, it makes sense to forego the faster memory. Finally, memory banks must be filled in pairs since it has two controllers. 

The connection between the North and South bridges is an updated version of IHA (Intel Hub Architecture) that was introduced with the i810 chipset. The E7500 has three HI 2.0 (Hub Interface) connections going out from the MCH. Each connection is 2 bytes wide and runs at 533 MHz, providing 1.06 GB/s bandwidth to devices. These links connect to 3 Intel P64H2 PCI/PCI-X controllers, each of which has two 64-bit, 133 MHz PCI/PCI-X buses. Incidentally, these three HI 2.0 links also total up to a bandwidth of 3.2 GB/s. 

The South bridge or the I/O Controller Hub (ICH) connects to the MCH using HI 1.5, an 8-bit wide bus running at 266 MHz, thus giving a total bandwidth of 266 MB/s. It has support for 6 USB 1.1 ports, 4 ATA-100 drives, 10/100 LAN controller and AC97 audio. 

Anuj Jain

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